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Jul 31, 2023

The future transistors

Nature volume 620, pages 501–515 (2023)Cite this article 9499 Accesses 33 Altmetric Metrics details The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary

Nature volume 620, pages 501–515 (2023)Cite this article

9499 Accesses

33 Altmetric

Metrics details

The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of complementary metal–oxide–semiconductor (CMOS) technology, represents one of the most momentous inventions since the industrial revolution. Driven by the requirements for higher speed, energy efficiency and integration density of integrated-circuit products, in the past six decades the physical gate length of MOSFETs has been scaled to sub-20 nanometres. However, the downscaling of transistors while keeping the power consumption low is increasingly challenging, even for the state-of-the-art fin field-effect transistors. Here we present a comprehensive assessment of the existing and future CMOS technologies, and discuss the challenges and opportunities for the design of FETs with sub-10-nanometre gate length based on a hierarchical framework established for FET scaling. We focus our evaluation on identifying the most promising sub-10-nanometre-gate-length MOSFETs based on the knowledge derived from previous scaling efforts, as well as the research efforts needed to make the transistors relevant to future logic integrated-circuit products. We also detail our vision of beyond-MOSFET future transistors and potential innovation opportunities. We anticipate that innovations in transistor technologies will continue to have a central role in driving future materials, device physics and topology, heterogeneous vertical and lateral integration, and computing technologies.

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K.B. acknowledges support from the Army Research Office (grant W911NF1810366), the Air Force Office of Scientific Research (grant FA9550-18-1-0448), the Japan Science and Technology Agency CREST Program (grant SB180064) and the National Science Foundation (grant CCF 2132820). K.B. thanks the following individuals for their selfless support during the organization of the collaboration: T. Ernst, CEA-LETI, Grenoble, France; T. Sakurai, The University of Tokyo, Tokyo, Japan; J. Welser, IBM Almaden Research Centre, San Jose, USA. K.B. also thanks S. Oda, Tokyo Institute of Technology, Ōokayama, Japan, for useful discussions.

Department of Electrical and Computer Engineering, University of California Santa Barbara, Santa Barbara, CA, USA

Wei Cao & Kaustav Banerjee

Advanced Logic and Memory Technology, IBM Research, Albany, NY, USA

Huiming Bu

Université Grenoble Alpes, CEA-LETI, Grenoble, France

Maud Vinet

Pathfinding, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan

Min Cao

Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan

Shinichi Takagi

Samsung Advanced Institute of Technology, Suwon-si, Korea

Sungwoo Hwang

Pathfinding and Technology Definition, Intel Corporation, Hillsboro, OR, USA

Tahir Ghani

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K.B. organized and led the collaboration. W.C. and K.B. wrote the paper with input from all other authors.

Correspondence to Kaustav Banerjee.

The authors declare no competing interests.

Nature thanks the anonymous reviewers for their contribution to the peer review of this work.

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Cao, W., Bu, H., Vinet, M. et al. The future transistors. Nature 620, 501–515 (2023). https://doi.org/10.1038/s41586-023-06145-x

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Received: 19 August 2020

Accepted: 27 April 2023

Published: 16 August 2023

Issue Date: 17 August 2023

DOI: https://doi.org/10.1038/s41586-023-06145-x

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